E-4
GUIDELINES FOR WRITING FPU EXCEPTIONS HANDLERS
compatibility mode. The actions of these mechanisms are slightly different and more straight-
forward for the P6 family processors, as described in Section E.2.2., MS-DOS* Compatibility
Mode in the P6 Family Processors.
For Pentium
®
and P6 family processors, it is important to note that the special DP (Dual Pro-
cessing) mode for Pentium
®
processors and also the more general Intel MultiProcessor Specifi-
cation for systems with multiple Pentium
®
or P6 family processors support FPU exception
handling only in the native mode. Intel does not recommend using the MS-DOS compatibility
FPU mode for systems using more than one processor.
E.2.1.1.BASIC RULES: WHEN FERR# IS GENERATED
When MS-DOS compatibility mode is enabled for the Intel486 or Pentium
®
processors (NE
bit is set to 0) and the IGNNE# input pin is de-asserted, the FERR# signal is generated as fol-
lows:
1.When an FPU instruction causes an unmasked FPU exception, the processor (in most
cases) uses a deferred method of reporting the error. This means that the processor does
not respond immediately, but rather freezes just before executing the next WAIT or FPU
instruction (except for no-wait instructions, which the FPU executes regardless of an
error condition).
2.When the processor freezes, it also asserts the FERR# output.
3.The frozen processor waits for an external interrupt, which must be supplied by external
hardware in response to the FERR# assertion.
4.In MS-DOS* compatibility systems, FERR# is fed to the IRQ13 input in the cascaded PIC.
The PIC generates interrupt 75H, which then branches to interrupt 2, as described earlier in
this appendix for systems using the Intel 286 and Intel 287 or Intel386 and Intel 387
processors.
The deferred method of error reporting is used for all exceptions caused by the basic arithmetic
instructions (including FADD, FSUB, FMUL, FDIV, FSQRT, FCOM and FUCOM), for preci-
sion exceptions caused by all types of FPU instructions, and for numeric underflow and over-
flow exceptions caused by all types of FPU instructions except stores to memory.
Some FPU instructions with some FPU exceptions use an immediate method of reporting er-
rors. Here, the FERR# is asserted immediately, at the time that the exception occurs. The imme-
diate method of error reporting is used for FPU stack fault, invalid operation and denormal
exceptions caused by all transcendental instructions, FSCALE, FXTRACT, FPREM and others,
and all exceptions (except precision) when caused by FPU store instructions. Like deferred error
reporting, immediate error reporting will cause the processor to freeze just before executing the
next WAIT or FPU instruction if the error condition has not been cleared by that time.
Note that in general, whether deferred or immediate error reporting is used for an FPU exception
depends both on which exception occurred and which instruction caused that exception. A com-
plete specification of these cases, which applies to both the Pentium
®
and the Intel486 pro-
cessors, is given in Section 5.1.2.1., Program-Error Exceptions, in Chapter 5, Interrupt and
Exception Handling, of the Intel Architecture Software Developers Manual, Volume 3.
