7-58
FLOATING-POINT UNIT
example, dividing an SNaN by zero can potentially signal an invalid-arithmetic-operand excep-
tion (due to the SNaN operand) and a divide-by-zero exception. Here, if both exceptions are
masked, the FPU handles the higher-priority exception only (the invalid-arithmetic-operand
exception), returning a real indefinite to the destination. Alternately, a denormal operand or
inexact result exception can accompany a numeric underflow or overflow exception, with both
exceptions being handled.
The precedence for floating-point exceptions is as follows:
1.Invalid operation exception, subdivided as follows:
a.Stack underflow.
b.Stack overflow.
c.Operand of unsupported format.
d.SNaN operand.
2.QNaN operand. Though this is not an exception, the handling of a QNaN operand has
precedence over lower-priority exceptions. For example, a QNaN divided by zero results
in a QNaN, not a zero-divide exception.
3.Any other invalid operation exception not mentioned above or a divide-by-zero exception.
4.Denormal operand exception. If masked, then instruction execution continues, and a
lower-priority exception can occur as well.
5.Numeric overflow and underflow exceptions in conjunction with the inexact result
exception.
6.Inexact result exception.
Invalid operation, zero divide, and denormal operand exceptions are detected before a floating-
point operation begins, whereas overflow, underflow, and precision errors are not detected until
a true result has been computed. When a pre-operation exception is detected, the FPU register
stack and memory have not yet been updated, and appear as if the offending instructions has not
been executed. When a post-operation exception is detected, the register stack and memory
may be updated with a result (depending on the nature of the error).
For more information on the order in which multiple exceptions or interrupts are serviced, refer
to Section 5.7., Priority Among Simultaneous Exceptions and Interrupts, in Chapter 5, Inter-
rupt and Exception Handling, of the Intel Architecture Software Developers Manual, Volume 3.
7.9.FLOATING-POINT EXCEPTION SYNCHRONIZATION
Because the integer unit and FPU are separate execution units, it is possible for the processor to
execute floating-point, integer, and system instructions concurrently. No special programming
techniques are required to gain the advantages of concurrent execution. (Floating-point instruc-
tions are placed in the instruction stream along with the integer and system instructions.)
However, concurrent execution can cause problems for floating-point exception handlers.
