F-1
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION
APPENDIX F
GUIDELINES FOR WRITING SIMD FLOATING-
POINT EXCEPTION HANDLERS
Most of the information on Streaming SIMD Extensions instructions can be found in Chapter 9,
Programming with the Streaming SIMD Extensions. Exceptions in Streaming SIMD Extensions
are specifically presented in Section 9.5.5., Exception Handling in Streaming SIMD Exten-
sions
This appendix considers only the Streaming SIMD Extensions instructions that can generate nu-
meric (floating-point) exceptions, and gives an overview of the necessary support for handling
such exceptions. This appendix does not address RSQRTSS, RSQRTPS, RCPSS, RCPPS, or
any unlisted instruction. For detailed information on which instructions generate numeric excep-
tions, and a listing of those exceptions, refer to Appendix D, SIMD Floating-Point Exceptions
Summary. Non-numeric exceptions are handled in a way similar to that for the standard IA-32
instructions.
F.1.TWO OPTIONS FOR HANDLING NUMERIC EXCEPTIONS
Just as for FPU floating-point exceptions, the processor takes one of two possible courses of ac-
tion when a Streaming SIMD Extensions instruction raises a floating-point exception.
If the exception being raised is masked (by setting the corresponding mask bit in the
MXCSR to 1), then a default result is produced, which is acceptable in most situations. No
external indication of the exception is given, but the corresponding exception flags in the
MXCSR are set, and may be examined later. Note though that for packed operations, an
exception flag that is set in the MXCSR will not tell which of the four sets of sub-operands
caused the event to occur.
If the exception being raised is not masked (by setting the corresponding mask bit in the
MXCSR to 0), a software exception handler previously registered by the user will be
invoked through the SIMD floating-point exception vector 19. This case is discussed
below in Section F.2., Software Exception Handling.
F.2.SOFTWARE EXCEPTION HANDLING
The exception handling routine reached via interrupt vector 19 is usually part of the system soft-
ware (the operating system kernel). Note that an interrupt descriptor table (IDT) entry must have
been previously set up for this vector (refer to Chapter 5, Interrupt and Exception Handling, in
the Intel Architecture Software Developers Manual, Volume 3). Some compilers use specific
run-time libraries to assist in floating-point exception handling. If any FPU floating-point oper-
ations are going to be performed that might raise floating-point exceptions, then the exception
handling routine must either disable all floating-point exceptions (for example, loading a local
