9-3
PROGRAMMING WITH THE STREAMING SIMD EXTENSIONS
MMX registers are mapped onto the floating-point registers. Transitioning from MMX
operations to floating-point operations required executing the EMMS instruction. Since SIMD
floating-point registers are a separate register file, MMX instructions and floating-point
instructions can be mixed with Streaming SIMD Extensions without execution of a special
instruction such as EMMS.
9.1.2.SIMD Floating-Point Data Types
The principal data type of the IA Streaming SIMD Extensions is a packed, single-precision,
floating-point operand, specifically:
Four 32-bit single-precision (SP), floating-point numbers (Figure 9-2)
The new SIMD-integer instructions will operate on the packed byte, word or doubleword data
types. The new prefetch instruction works on typeless data of size 32 bytes or greater.
Figure 9-1. SIMD Floating-Point Registers
Figure 9-2. Packed Single-FP
XMM7
XMM6
XMM5
XMM4
XMM3
XMM2
XMM1
XMM0
Packed Single-FP
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