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BASIC EXECUTION ENVIRONMENT
flag; the processor only reads it.) Used in conjunction with the VIF
flag.
ID (bit 21)
Identification flag. The ability of a program to set or clear this flag
indicates support for the CPUID instruction.
Refer to Chapter 3, Protected-Mode Memory Management, in the Intel Architecture Software
Developers Manual, Volume 3, for a detail description of these flags.
3.7.INSTRUCTION POINTER
The instruction pointer (EIP) register contains the offset in the current code segment for the next
instruction to be executed. It is advanced from one instruction boundary to the next in straight-
line code or it is moved ahead or backwards by a number of instructions when executing JMP,
Jcc, CALL, RET, and IRET instructions.
The EIP register cannot be accessed directly by software; it is controlled implicitly by control-
transfer instructions (such as JMP, Jcc, CALL, and RET), interrupts, and exceptions. The only
way to read the EIP register is to execute a CALL instruction and then read the value of the
return instruction pointer from the procedure stack. The EIP register can be loaded indirectly by
modifying the value of a return instruction pointer on the procedure stack and executing a return
instruction (RET or IRET). Refer to Section 4.2.4.2., Return Instruction Pointer in Chapter 4,
Procedure Calls, Interrupts, and Exceptions.
All IA processors prefetch instructions. Because of instruction prefetching, an instruction
address read from the bus during an instruction load does not match the value in the EIP register.
Even though different processor generations use different prefetching mechanisms, the function
of EIP register to direct program flow remains fully compatible with all software written to run
on IA processors.
3.8.OPERAND-SIZE AND ADDRESS-SIZE ATTRIBUTES
When the processor is executing in protected mode, every code segment has a default operand-
size attribute and address-size attribute. These attributes are selected with the D (default size)
flag in the segment descriptor for the code segment (refer to Chapter 3, Protected-Mode Memory
Management, in the Intel Architecture Software Developers Manual, Volume 3). When the D
flag is set, the 32-bit operand-size and address-size attributes are selected; when the flag is clear,
the 16-bit size attributes are selected. When the processor is executing in real-address mode,
virtual-8086 mode, or SMM, the default operand-size and address-size attributes are always 16
bits.
The operand-size attribute selects the sizes of operands that instructions operate on. When the
16-bit operand-size attribute is in force, operands can generally be either 8 bits or 16 bits, and
when the 32-bit operand-size attribute is in force, operands can generally be 8 bits or 32 bits.
The address-size attribute selects the sizes of addresses used to address memory: 16 bits or 32
bits. When the 16-bit address-size attribute is in force, segment offsets and displacements are 16
bits. This restriction limits the size of a segment that can be addressed to 64 KBytes. When the
