7-21
FLOATING-POINT UNIT
Software cannot directly load or modify the tags in the tag register. The FLDENV and FRSTOR
instructions load an image of the tag register into the FPU; however, the FPU uses those tag
values only to determine if the data registers are empty (11B) or non-empty (00B, 01B, or 10B).
If the tag register image indicates that a data register is empty, the tag in the tag register for that
data register is marked empty (11B); if the tag register image indicates that the data register is
non-empty, the FPU reads the actual value in the data register and sets the tag for the register
accordingly. This action prevents a program from setting the values in the tag register to incor-
rectly represent the actual contents of non-empty data registers.
7.3.7.FPU Instruction and Operand (Data) Pointers
The FPU stores pointers to the instruction and operand (data) for the last non-control instruction
executed in two 48-bit registers: the FPU instruction pointer and FPU operand (data) pointer
registers (refer to Figure 7-5). (This information is saved to provide state information for excep-
tion handlers.)
The contents of the FPU instruction and operand pointer registers remain unchanged when any
of the control instructions (FINIT/FNINIT, FCLEX/FNCLEX, FLDCW, FSTCW/FNSTCW,
FSTSW/FNSTSW, FSTENV/FNSTENV, FLDENV, FSAVE/FNSAVE, FRSTOR, and
WAIT/FWAIT) are executed. The contents of the FPU operand register are undefined if the prior
non-control instruction did not have a memory operand.
The pointers stored in the FPU instruction and operand pointer registers consist of an offset
(stored in bits 0 through 31) and a segment selector (stored in bits 32 through 47).
These registers can be accessed by the FSTENV/FNSTENV, FLDENV, FINIT/FNINIT,
FSAVE/FNSAVE and FRSTOR instructions. The FINIT/FNINIT and FSAVE/FNSAVE instruc-
tions clear these registers.
For all the IA FPUs and NPXs except the 8087, the FPU instruction pointer points to any
prefixes that preceded the instruction. For the 8087, the FPU instruction pointer points only to
the actual opcode.
7.3.8.Last Instruction Opcode
The FPU stores the opcode of the last non-control instruction executed in an 11-bit FPU opcode
register. (This information provides state information for exception handlers.) Only the first and
second opcode bytes (after all prefixes) are stored in the FPU opcode register. Figure 7-12 shows
the encoding of these two bytes. Since the upper 5 bits of the first opcode byte are the same for
all floating-point opcodes (11011B), only the lower 3 bits of this byte are stored in the opcode
register.
7.3.9.Saving the FPUs State
The FSTENV/FNSTENV and FSAVE/FNSAVE instructions store FPU state information in
memory for use by exception handlers and other system and application software. The
