E-12
GUIDELINES FOR WRITING FPU EXCEPTIONS HANDLERS
becomes zero. With the divide-by-zero and precision exceptions masked, the processor will pro-
duce the correct result. FDIV of R1 into 1 gives infinity, and then FDIV of (infinity +R2 +R3)
into 1 gives zero.
By masking or unmasking specific numeric exceptions in the FPU control word, programmers
can delegate responsibility for most exceptions to the processor, reserving the most severe ex-
ceptions for programmed exception handlers. Exception-handling software is often difficult to
write, and the masked responses have been tailored to deliver the most reasonable result for each
condition. For the majority of applications, masking all exceptions yields satisfactory results
with the least programming effort. Certain exceptions can usefully be left unmasked during the
debugging phase of software development, and then masked when the clean software is actually
run. An invalid operation exception for example, typically indicates a program error that must
be corrected.
The exception flags in the FPU status word provide a cumulative record of exceptions that have
occurred since these flags were last cleared. Once set, these flags can be cleared only by execut-
ing the FCLEX/FNCLEX (clear exceptions) instruction, by reinitializing the FPU with
FINIT/FNINIT or FSAVE/FNSAVE, or by overwriting the flags with an FRSTOR or FLDENV
instruction. This allows a programmer to mask all exceptions, run a calculation, and then inspect
the status word to see if any exceptions were detected at any point in the calculation.
E.3.2.2.SOFTWARE EXCEPTION HANDLING
If the FPU in or with an IA processor (Intel 286 and onwards) encounters an unmasked excep-
tion condition, with the system operated in the MS-DOS compatibility mode and with IGNNE#
not asserted, a software exception handler is invoked through a PIC and the processors INTR
pin. The FERR# (or ERROR#) output from the FPU that begins the process of invoking the ex-
ception handler may occur when the error condition is first detected, or when the processor en-
counters the next WAIT or FPU instruction. Which of these two cases occurs depends on the
processor generation and also on which exception and which FPU instruction triggered it, as dis-
Figure E-4. Arithmetic Example Using Infinity
Equivalent Resistance =
1
1
R
1
+
+
R
1
1
R
2
1
R
3
R
2
R
3
