E-7
GUIDELINES FOR WRITING FPU EXCEPTIONS HANDLERS
circuit does not depend on the order of actions by the FPU exception handler to guarantee the
correct hardware state upon exit from the handler. Flip Flop #2, which drives IGNNE# to the
processor, has its CLEAR input attached to the inverted FERR#. This ensures that IGNNE# can
never be active when FERR# is inactive. So if the handler clears the FPU exception condition
before the 0F0H access, IGNNE# does not get activated and left on after exit from the handler.
E.2.1.3.NO-WAIT FPU INSTRUCTIONS CAN GET FPU INTERRUPT IN
WINDOW
The Pentium
®
and Intel486 processors implement the no-wait floating-point instructions
(FNINIT, FNCLEX, FNSTENV, FNSAVE, FNSTSW, FNSTCW, FNENI, FNDISI or
FNSETPM) in the MS-DOS compatibility mode in the following manner. (Refer to Section
7.5.11., FPU Control Instructions and Section 7.5.12., Waiting Vs. Non-waiting Instruc-
tions in Chapter 7, Floating-Point Unit, for a discussion of the no-wait instructions.)
If an unmasked numeric exception is pending from a preceding FPU instruction, a member of
the no-wait class of instructions will, at the beginning of its execution, assert the FERR# pin in
response to that exception just like other FPU instructions, but then, unlike the other FPU in-
structions, FERR# will be de-asserted. This de-assertion was implemented to allow the no-wait
class of instructions to proceed without an interrupt due to any pending numeric exception.
However, the brief assertion of FERR# is sufficient to latch the FPU exception request into most
hardware interface implementations (including Intels recommended circuit).
All the FPU instructions are implemented such that during their execution, there is a window in
which the processor will sample and accept external interrupts. If there is a pending interrupt,
the processor services the interrupt first before resuming the execution of the instruction. Con-
sequently, it is possible that the no-wait floating-point instruction may accept the external inter-
rupt caused by its own assertion of the FERR# pin in the event of a pending unmasked numeric
Figure E-2. Behavior of Signals During FPU Exception Handling
0F0H Address
Decode
