6-45
INSTRUCTION SET SUMMARY
registers before the execution of string instructions or for initializing the EBX register before an
XLAT instruction.
6.15.2.Table Lookup Instructions
The XLAT and XLATB (table lookup) instructions replace the contents of the AL register with
a byte read from a translation table in memory. The initial value in the AL register is interpreted
as an unsigned index into the translation table. This index is added to the contents of the EBX
register (which contains the base address of the table) to calculate the address of the table entry.
These instructions are used for applications such as converting character codes from one
alphabet into another (for example, an ASCII code could be used to look up its EBCDIC equiv-
alent in a table).
6.15.3.Processor Identification Instruction
The CPUID (processor identification) instruction provides information about the processor on
which the instruction is executed. To obtain processor information, a value of from 0 to 2 is
loaded in the EAX register and then the CPUID instruction is executed. The resulting processor
information is placed in the EAX, EBX, ECX, and EDX registers. Table 6-5 shows the informa-
tion that is provided depending on the value initially entered in the EAX register. Refer to
Section 11.1., Processor Identification in Chapter 11, Processor Identification and Feature
Determination for detailed information on the output of the CPUID instruction.
6.15.4.No-Operation and Undefined Instructions
The NOP (no operation) instruction increments the EIP register to point at the next instruction,
but affects nothing else.
The UD2 (undefined) instruction generates an invalid opcode exception. Intel reserves the
opcode for this instruction for this function. The instruction is provided to allow software to test
an invalid opcode exception handler.
Table 6-5. Information Provided by the CPUID Instruction
Initial EAX Value
Information Provided about the Processor
0
Maximum CPUID input value.
Vendor identification string (GenuineIntel).
1
Version information (family ID, model ID, and stepping ID).
Feature information (identifies the feature set for the processor model).
2
Cache information (about the processors internal cache memory).
