3-10
BASIC EXECUTION ENVIRONMENT
The four segment registers CS, DS, SS, and ES are the same as the segment registers found in
the Intel 8086 and Intel 286 processors and the FS and GS registers were introduced into the IA
with the Intel386 family of processors.
3.6.3.EFLAGS Register
The 32-bit EFLAGS register contains a group of status flags, a control flag, and a group of
system flags. Figure 3-7 defines the flags within this register. Following initialization of the
processor (either by asserting the RESET pin or the INIT pin), the state of the EFLAGS register
is 00000002H. Bits 1, 3, 5, 15, and 22 through 31 of this register are reserved. Software should
not use or depend on the states of any of these bits.
Some of the flags in the EFLAGS register can be modified directly, using special-purpose
instructions (described in the following sections). There are no instructions that allow the whole
register to be examined or modified directly. However, the following instructions can be used to
move groups of flags to and from the procedure stack or the EAX register: LAHF, SAHF,
PUSHF, PUSHFD, POPF, and POPFD. After the contents of the EFLAGS register have been
transferred to the procedure stack or EAX register, the flags can be examined and modified using
the processors bit manipulation instructions (BT, BTS, BTR, and BTC).
When suspending a task (using the processors multitasking facilities), the processor automati-
cally saves the state of the EFLAGS register in the task state segment (TSS) for the task being
suspended. When binding itself to a new task, the processor loads the EFLAGS register with
data from the new tasks TSS.
When a call is made to an interrupt or exception handler procedure, the processor automatically
saves the state of the EFLAGS registers on the procedure stack. When an interrupt or exception
is handled with a task switch, the state of the EFLAGS register is saved in the TSS for the task
being suspended.
