F-7
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION
Section 5.7., Priority Among Simultaneous Exceptions and Interrupts in Chapter 5, Interrupt
and Exception Handling.
Note that some floating-point instructions (non-waiting instructions) do not check for pending
unmasked exceptions (refer to Section 7.5.11., FPU Control Instructions, in Chapter 7,
Floating-Point Unit). They include the FNINIT, FNSTENV, FNSAVE, FNSTSW, FNSTCW,
and FNCLEX instructions. When an FNINIT, FNSTENV, FNSAVE, or FNCLEX instruction is
executed, all pending exceptions are essentially lost (either the FPU status register is cleared or
all exceptions are masked). The FNSTSW and FNSTCW instructions do not check for pending
interrupts, but they do not modify the FPU status and control registers. A subsequent waiting
floating-point instruction can then handle any pending exceptions.
F.4.2.1.NUMERIC EXCEPTIONS
There are six classes of numeric (floating-point) exception conditions that can occur: Invalid op-
eration (#I), Divide-by-Zero (#Z), Denormal Operand (#D), Numeric Overflow (#O), Numeric
Underflow (#U), and Inexact Result (precision) (#P). #I, #Z, #D are pre-computation exceptions
(floating-point faults), detected before the arithmetic operation. #O, #U, #P are post-computa-
tion exceptions (floating-point traps).
Users can control how the exceptions are handled by setting the mask/unmask bits in MXCSR.
Masked exceptions are handled by the processor or by software if they are combined with un-
masked exceptions occurring in the same instruction. Unmasked exceptions are usually handled
by the low-level exception handler, in conjunction with user-level software.
F.4.2.2.RESULTS OF OPERATIONS WITH NAN OPERANDS OR A NAN
RESULT FOR STREAMING SIMD EXTENSIONS NUMERIC
INSTRUCTIONS
The tables below specify the response of the Streaming SIMD Extensions technology instruc-
tions to NaN inputs, or to other inputs that lead to NaN results.
These results will be referenced by subsequent tables. Most operations do not raise an invalid
exception for quiet NaN operands, but even so, they will have higher precedence over raising
some exception.
Note that the single-precision QNaN Indefinite value is 0xffc00000, and the Integer Indefinite
value is 0x80000000 (not a floating-point number, but it can be the result of a conversion in-
struction from floating-point to integer).
For an unmasked exception, no result will be provided to the user handler. If a user registered
floating-point exception handler is invoked, it may provide a result for the excepting instruction,
that will be used if execution of the application code is continued after returning from the inter-
ruption.
In Tables F-1 through Table F-10, the specified operands cause an invalid exception, unless the
unmasked result is marked with (not an exception). In this latter case, the unmasked and
masked results are the same.
