1-5
ABOUT THIS MANUAL
Chapter 15 Debugging and Performance Monitoring. Describes the debugging registers
and other debug mechanism provided in the IA. This chapter also describes the time-stamp
counter and the performance-monitoring counters.
Chapter 16 8086 Emulation. Describes the real-address and virtual-8086 modes of the IA.
Chapter 17 Mixing 16-Bit and 32-Bit Code. Describes how to mix 16-bit and 32-bit code
modules within the same program or task.
Chapter 18 Intel Architecture Compatibility. Describes the programming differences
between the Intel 286, Intel386, Intel486, Pentium
®
, and P6 family processors. The differ-
ences among the 32-bit IA processors (the Intel386, Intel486, Pentium
®
, and P6 family
processors) are described throughout the three volumes of the Intel Architecture Software Devel-
opers Manual, as relevant to particular features of the architecture. This chapter provides a
collection of all the relevant compatibility information for all IA processors and also describes
the basic differences with respect to the 16-bit IA processors (the Intel 8086 and Intel 286
processors).
Appendix A Performance-Monitoring Events. Lists the events that can be counted with
the performance-monitoring counters and the codes used to select these events. Both Pentium
®
processor and P6 family processor events are described.
Appendix B Model-Specific Registers (MSRs). Lists the MSRs available in the Pentium
®
and P6 family processors and their functions.
Appendix C Dual-Processor (DP) Bootup Sequence Example (Specific to Pentium
®
Processors). Gives an example of how to use the DP protocol to boot two Pentium
®
processors
(a primary processor and a secondary processor) in a DP system and initialize their APICs.
Appendix D Multiple-Processor (MP) Bootup Sequence Example (Specific to P6 Family
Processors). Gives an example of how to use of the MP protocol to boot two P6 family proces-
sors in a MP system and initialize their APICs.
Appendix E Programming the LINT0 and LINT1 Inputs. Gives an example of how to
program the LINT0 and LINT1 pins for specific interrupt vectors.
1.4.NOTATIONAL CONVENTIONS
This manual uses special notation for data-structure formats, for symbolic representation of
instructions, and for hexadecimal numbers. A review of this notation makes the manual easier
to read.
1.4.1.Bit and Byte Order
In illustrations of data structures in memory, smaller addresses appear toward the bottom of the
figure; addresses increase toward the top. Bit positions are numbered from right to left. The
numerical value of a set bit is equal to two raised to the power of the bit position. IA processors
are little endian machines; this means the bytes of a word are numbered starting from the least
significant byte. Figure 1-1 illustrates theseconventions.
