6-3
INSTRUCTION SET SUMMARY
6.1.5.New Instructions in the Intel486 Processor
The following instructions are new in the Intel486 processor:
BSWAP (byte swap) instruction.
XADD (exchange and add) instruction.
CMPXCHG (compare and exchange) instruction.
?
NVD (invalidate cache) instruction.
WBINVD (write-back and invalidate cache) instruction.
INVLPG (invalidate TLB entry) instruction.
6.2.INSTRUCTION SET LIST
This section lists all the IA instructions divided into three major groups: integer, MMX tech-
nology, floating-point, and system instructions. For each instruction, the mnemonic and descrip-
tive names are given. When two or more mnemonics are given (for example,
CMOVA/CMOVNBE), they represent different mnemonics for the same instruction opcode.
Assemblers support redundant mnemonics for some instructions to make it easier to read code
listings. For instance, CMOVA (Conditional move if above) and CMOVNBE (Conditional
move is not below or equal) represent the same condition.
6.2.1.Integer Instructions
Integer instructions perform the integer arithmetic, logic, and program flow control operations
that programmers commonly use to write application and system software to run on an IA
processor. In the following sections, the integer instructions are divided into several instruction
subgroups.
6.2.1.1.DATA TRANSFER INSTRUCTIONS
MOV
Move
CMOVE/CMOVZ
Conditional move if equal/Conditional move if zero
CMOVNE/CMOVNZConditional move if not equal/Conditional move if not zero
CMOVA/CMOVNBEConditional move if above/Conditional move if not below
or equal
CMOVAE/CMOVNBConditional move if above or equal/Conditional move if
not below
CMOVB/CMOVNAEConditional move if below/Conditional move if not above
or equal
CMOVBE/CMOVNAConditional move if below or equal/Conditional move if not above
