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INTRODUCTION TO THE INTEL ARCHITECTURE
executed but not yet committed to machine state. The dispatch/execute unit can execute instruc-
tions from the reorder buffer in any order.
2.5.4.Dispatch/Execute Unit
The dispatch/execute unit is an out-of-order unit that schedules and executes the micro-ops
stored in the reorder buffer according to data dependencies and resource availability and tempo-
rarily stores the results of these speculative executions.
The scheduling and dispatching of micro-ops from the reorder buffer is handled by the reserva-
tion station. It continuously scans the reorder buffer for micro-ops that are ready to be executed
(that is, all the source operands are available) and dispatches them to the available execution
units. The results of a micro-op execution are returned to the reorder buffer and stored along
with the micro-op until it is retired. This scheduling and dispatching process supports classic
out-of-order execution, where micro-ops are dispatched to the execution units strictly according
to data-flow constraints and execution resource availability, without regard to the original
ordering of the instructions. When two or more micro-ops of the same type (for example, integer
operations) are available at the same time, they are executed in a pseudo FIFO order in the
reorder buffer.
Execution of micro-ops is handled by two integer units, two floating-point units, and one
memory-interface unit, allowing up to five micro-ops to be scheduled per clock.
The two integer units can handle two integer micro-ops in parallel. One of the integer units is
designed to handle branch micro-ops. This unit has the ability to detect branch mispredictions
and signal the branch target buffer to restart the pipeline. This operation is handled as follows.
The instruction decoder tags each branch micro-op with both branch destination addresses (the
predicted destination and the fall-through destination). When the integer unit executes the
branch micro-op, it is able to determine whether the predicted or the fall-through destination was
taken. If the predicted branch is taken, then speculatively executed micro-ops are marked usable
and execution continues along the predicted instruction path. If the predicted branch was not
taken, a jump execution unit in the integer unit changes the status of all of the micro-ops
following the branch to remove them from the instruction pool. It then provides the proper
branch destination to the branch target buffer, which in turn restarts the pipeline from the new
target address.
The memory interface unit handles load and store micro-ops. A load access only needs to
specify the memory address, so it can be encoded in one micro-op. A store access needs to
specify both an address and the data to be written, so it is encoded in two micro-ops. The part of
the memory interface unit that handles stores has two ports allowing it to process the address
and the data micro-op in parallel. The memory interface unit can thus execute both a load and a
store in parallel in one clock cycle.
The floating-point execution units are similar to those found in the Pentium
®
processor. Several
new floating-point instructions have been added to the P6 Family processor to streamline condi-
tional branches and moves.
