7.8.5.Numeric Underflow Exception (#U)
The FPU reports a floating-point numeric underflow exception (#U) whenever the rounded
result of an arithmetic instruction is tiny (that is, less than the smallest possible normalized,
finite value that will fit into the real format of the destination operand). For example, if the desti-
nation format is extended-real (80 bits), underflow occurs when the rounded result falls in the
unbiased range of
?
1.0
?
2
?
16382
to 1.0
?
2
?
16382
(exclusive). Like numeric overflow, numeric
underflow can occur on arithmetic operations where the result is stored in an FPU data register.
It can also occur on store-real operations (with the FST and FSTP instructions), where a within-
range value in a data register is stored in memory in a single- or double-real format. The under-
flow threshold range for the single-real format is
?
1.0
?
2
?
126
to 1.0
?
2
?
126
; the range for the
double-real format is
?
1.0
?
2
?
1022
to 1.0
?
2
?
1022
. (The numeric underflow exception cannot
occur when storing values in an integer or BCD integer format.)
The flag (UE) for the numeric-underflow exception is bit 4 of the FPU status word, and the mask
bit (UM) is bit 4 of the FPU control word.
When a numeric-underflow exception occurs and the exception is masked, the FPU denormal-
izes the result (refer to Section 7.2.3.2., Normalized and Denormalized Finite Numbers). If
the denormalized result is exact, the FPU stores the result in the destination operand, without
setting the UE flag. If the denormal result is inexact, the FPU sets the UE flag, then goes on to
handle the inexact result exception condition (refer to Section 7.8.6., Inexact Result (Precision)
Exception (#P)). It is important to note that if numeric-underflow is masked, a numeric-under-
flow exception is signaled only if the denormalized result is inexact. If the denormalized result
is exact, no flags are set and no exceptions are signaled.
The action that the FPU takes when numeric underflow occurs and the numeric-underflow
exception is not masked, depends on whether the instruction is supposed to store the result in
memory or on the register stack.
If the destination is a memory location, the UE flag is set and a software exception handler is
invoked (refer to Section 7.7.3., Software Exception Handling). The top-of-stack pointer
(TOP) and source and destination operands remain unchanged.
If the destination is the register stack, the exponent of the rounded result is multiplied by
2
24576
and the product is stored along with the significand in the destination operand. Condition
code bit C1 in the FPU the status register (acting here as a round-up bit) is set if the significand
was rounded upward and cleared if the result was rounded toward 0. After the result is stored,
the UE flag is set and a software exception handler is invoked.
The scaling bias value 24,576 is the same as is used for the overflow exception and has the same
effect, which is to translate the result as nearly as possible to the middle of the extended-real
exponent range.
When using the FSCALE instruction, massive underflow can occur, where the result is too tiny
to be represented, even with a bias-adjusted exponent. Here, if underflow occurs again, after the
result has been biased, a properly signed 0 is stored in the destination operand.
