F-16
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION
static float quietf (float f); // converts a signaling NaN to a quiet NaN, and
// leaves a quiet NaN unchanged
// emulation of Streaming SIMD Extensions instructions using
// C code and IA-32 FPU instructions
unsigned int
simd_fp_emulate (EXC_ENV *exc_env)
{
float opd1; // first operand of the add, subtract, multiply, or divide
float opd2; // second operand of the add, subtract, multiply, or divide
float res; // result of the add, subtract, multiply, or divide
double dbl_res24; // result with 24-bit significand, but "unbounded" exponent
// (needed to check tininess, to provide a scaled result to
// an underflow/overflow trap handler, and in flush-to-zero mode)
double dbl_res; // result in double precision format (needed to avoid a
// double rounding error when denormalizing)
unsigned int result_tiny;
unsigned int result_huge;
unsigned short int sw; // 16 bits
unsigned short int cw; // 16 bits
// have to check first for faults (V, D, Z), and then for traps (O, U, I)
// initialize FPU (floating-point exceptions are masked)
_asm {
fninit;
}
result_tiny = 0;
result_huge = 0;
switch (exc_env->operation) {
case ADDPS:
case ADDSS:
case SUBPS:
case SUBSS:
case MULPS:
case MULSS:
case DIVPS:
case DIVSS:
