F-20
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION
exc_env->result_fval = res; // exact
exc_env->status_flag_invalid_operation = 1;
return (DO_NOT_RAISE_EXCEPTION);
}
// dbl_res24 is not a NaN at this point
if (sw & DENORMAL_MASK) exc_env->status_flag_denormal_operand = 1;
// Note: (dbl_res24 == 0.0 && sw & PRECISION_MASK) cannot occur
if (-MIN_SINGLE_NORMAL < dbl_res24 && dbl_res24 < 0.0 ||
0.0 < dbl_res24 && dbl_res24 < MIN_SINGLE_NORMAL) {
result_tiny = 1;
}
// check if the result is huge
if (NEGINFF < dbl_res24 && dbl_res24 < -MAX_SINGLE_NORMAL ||
MAX_SINGLE_NORMAL < dbl_res24 && dbl_res24 < POSINFF) {
result_huge = 1;
}
// at this point, there are no enabled I, D, or Z exceptions; the instr.
// might lead to an enabled underflow, enabled underflow and inexact,
// enabled overflow, enabled overflow and inexact, enabled inexact, or
// none of these; if there are no U or O enabled exceptions, re-execute
// the instruction using IA-32 double precision format, and the
// users rounding mode; exceptions must have been disabled before calling
// this function; an inexact exception may be reported on the 53-bit
// fsubp, fmulp, or on both the 53-bit and 24-bit conversions, while an
// overflow or underflow (with traps disabled) may be reported on the
// conversion from dbl_res to res
// check whether there is an underflow, overflow, or inexact trap to be
// taken
// if the underflow traps are enabled and the result is tiny, take
// underflow trap
if (!(exc_env->exc_masks & UNDERFLOW_MASK) && result_tiny) {
dbl_res24 = TWO_TO_192 * dbl_res24; // exact
exc_env->status_flag_underflow = 1;
exc_env->exception_cause = UNDERFLOW;
exc_env->result_fval = (float)dbl_res24; // exact
if (sw & PRECISION_MASK) exc_env->status_flag_inexact = 1;
return (RAISE_EXCEPTION);
}
// if overflow traps are enabled and the result is huge, take
