1-3
ABOUT THIS MANUAL
Chapter 10 Input/Output. Describes the processors I/O architecture, including I/O port
addressing, the I/O instructions, and the I/O protection mechanism.
Chapter 11 Processor Identification and Feature Determination. Describes how to deter-
mine the CPU type and the features that are available in the processor.
Appendix A EFLAGS Cross-Reference. Summarizes how the Intel Architecture instruc-
tions affect the flags in the EFLAGS register.
Appendix B EFLAGS Condition Codes. Summarizes how the conditional jump, move, and
byte set on condition code instructions use the condition code flags (OF, CF, ZF, SF, and PF) in
the EFLAGS register.
Appendix C Floating-Point Exceptions Summary. Summarizes the exceptions that can be
raised by floating-point instructions.
Appendix D SIMD Floating-Point Exceptions Summary. Provides the Streaming SIMD
Extensions mnemonics, and the exceptions that each instruction can cause.
Appendix E Guidelines for Writing FPU Exception Handlers. Describes how to design
and write MS-DOS* compatible exception handling facilities for FPU and SIMD floating-point
exceptions, including both software and hardware requirements and assembly-language code
examples. This appendix also describes general techniques for writing robust FPU exception
handlers.
Appendix F Guidelines for Writing SIMD-FP Exception Handlers. Provides guidelines
for the Streaming SIMD Extensions instructions that can generate numeric (floating-point)
exceptions, and gives an overview of the necessary support for handling such exceptions.
1.3.OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE
DEVELOPERS MANUAL, VOLUME 3: SYSTEM
PROGRAMMING GUIDE
The contents of the Intel Architecture Software Developers Manual, Volume 3, are as follows:
Chapter 1 About This Manual. Gives an overview of all three volumes of the Intel Archi-
tecture Software Developers Manual. It also describes the notational conventions in these
manuals and lists related Intel manuals and documentation of interest to programmers and hard-
ware designers.
Chapter 2 System Architecture Overview. Describes the modes of operation of an Intel
Architecture processor and the mechanisms provided in the Intel Architecture to support oper-
ating systems and executives, including the system-oriented registers and data structures and the
system-oriented instructions. The steps necessary for switching between real-address and
protected modes are also identified.
Chapter 3 Protected-Mode Memory Management. Describes the data structures, registers,
and instructions that support segmentation and paging and explains how they can be used to
implement a flat (unsegmented) memory model or a segmented memory model.
