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ABOUT THIS MANUAL
Chapter 4 Protection. Describes the support for page and segment protection provided in
the Intel Architecture. This chapter also explains the implementation of privilege rules, stack
switching, pointer validation, user and supervisor modes.
Chapter 5 Interrupt and Exception Handling. Describes the basic interrupt mechanisms
defined in the Intel Architecture, shows how interrupts and exceptions relate to protection, and
describes how the architecture handles each exception type. Reference information for each
Intel Architecture exception is given at the end of this chapter.
Chapter 6 Task Management. Describes the mechanisms the Intel Architecture provides to
support multitasking and inter-task protection.
Chapter 7 Multiple Processor Management. Describes the instructions and flags that
support multiple processors with shared memory, memory ordering, and the advanced program-
mable interrupt controller (APIC).
Chapter 8 Processor Management and Initialization. Defines the state of an Intel Archi-
tecture processor and its floating-point and SIMD floating-point units after reset initialization.
This chapter also explains how to set up an Intel Architecture processor for real-address mode
operation and protected- mode operation, and how to switch between modes.
Chapter 9 Memory Cache Control. Describes the general concept of caching and the
caching mechanisms supported by the Intel Architecture. This chapter also describes the
memory type range registers (MTRRs) and how they can be used to map memory types of phys-
ical memory. MTRRs were introduced into the Intel Architecture with the Pentium
®
Pro
processor. It also presents information on using the new cache control and memory streaming
instructions introduced with the Pentium
®
III processor.
Chapter 10 MMX Technology System Programming. Describes those aspects of the
Intel MMX technology that must be handled and considered at the system programming level,
including task switching, exception handling, and compatibility with existing system environ-
ments. The MMX technology was introduced into the Intel Architecture with the Pentium
®
processor.
Chapter 11 Streaming SIMD Extensions System Programming. Describes those aspects
of Streaming SIMD Extensions that must be handled and considered at the system programming
level, including task switching, exception handling, and compatibility with existing system
environments. Streaming SIMD Extensions were introduced into the Intel Architecture with the
Pentium
®
processor.
Chapter 12 System Management Mode (SMM). Describes the Intel Architectures system
management mode (SMM), which can be used to implement power management functions.
Chapter 13 Machine-Check Architecture. Describes the machine-check architecture,
which was introduced into the Intel Architecture with the Pentium
®
processor.
Chapter 14 Code Optimization. Discusses general optimization techniques for program-
ming an Intel Architecture processor.
Chapter 15 Debugging and Performance Monitoring. Describes the debugging registers
and other debug mechanism provided in the Intel Architecture. This chapter also describes the
time-stamp counter and the performance-monitoring counters.
