2-3
INSTRUCTION FORMAT
Certain encodings of the ModR/M byte require a second addressing byte, the SIB byte, to fully
specify the addressing form. The base-plus-index and scale-plus-index forms of 32-bit
addressing require the SIB byte. The SIB byte includes the following fields:
The scale field specifies the scale factor.
The index field specifies the register number of the index register.
The base field specifies the register number of the base register.
Refer to Section 2.6. for the encodings of the ModR/M and SIB bytes.
2.5.DISPLACEMENT AND IMMEDIATE BYTES
Some addressing forms include a displacement immediately following either the ModR/M or
SIB byte. If a displacement is required, it can be 1, 2, or 4 bytes.
If the instruction specifies an immediate operand, the operand always follows any displacement
bytes. An immediate operand can be 1, 2, or 4 bytes.
2.6.ADDRESSING-MODE ENCODING OF MODR/M AND SIB
BYTES
The values and the corresponding addressing forms of the ModR/M and SIB bytes are shown in
Tables 2-1 through 2-3. The 16-bit addressing forms specified by the ModR/M byteare in Table
2-1, and the 32-bit addressing forms specified by the ModR/M byte are in Table 2-2. Table 2-3
shows the 32-bit addressing forms specified by the SIB byte.
In Tables 2-1 and 2-2, the first column (labeled Effective Address) lists 32 different effective
addresses that can be assigned to one operand of an instruction by using the Mod and R/M fields
of the ModR/M byte. The first 24 give the different ways of specifying a memory location; the
last eight (specified by the Mod field encoding 11B) give the ways of specifying the general
purpose, MMX technology, and SIMD floating-point registers. Each of the register encodings
list five possible registers. For example, the first register-encoding (selected by the R/M field
encoding of 000B) indicates the general-purpose registers EAX, AX or AL, the MMX tech-
nology register MM0, or the SIMD floating-point register XMM0. Which of these five registers
is used is determined by the opcode byte and the operand-size attribute, which select either the
EAX register (32 bits) or AX register (16 bits).
The second and third columns in Tables 2-1 and 2-2 gives the binary encodings of the Mod and
R/M fields in the ModR/M byte, respectively, required to obtain the associated effective address
listed in the first column. All 32 possible combinations of the Mod and R/M fields are listed.
Across the top of Tables 2-1 and 2-2, the eight possible values of the 3-bit Reg/Opcode field are
listed, in decimal (sixth row from top) and in binary (seventh row from top). The seventh row is
labeled REG=, which represents the use of these three bits to give the location of a second
operand, which must be a general-purpose register, an MMX technology register, or a SIMD
floating-point register. If the instruction does not require a second operand to be specified, then
the 3 bits of the Reg/Opcode field may be used as an extension of the opcode, which is repre-
