2-2
INSTRUCTION FORMAT
Segment override.
2EHCS segment override prefix.
36HSS segment override prefix.
3EHDS segment override prefix.
26HES segment override prefix.
64HFS segment override prefix.
65HGS segment override prefix.
Operand-size override, 66H
Address-size override, 67H
For each instruction, one prefix may be used from each of these groups and be placed in any
order. The effect of redundant prefixes (more than one prefix from a group) is undefined and
may vary from processor to processor.
Streaming SIMD Extensions prefix, 0FH
The nature of Streaming SIMD Extensions allows the use of existing instruction formats.
Instructions use the ModR/M format and are preceded by the 0F prefix byte. In general, opera-
tions are not duplicated to provide two directions (i.e. separate load and store variants). For more
information, see Section B.4.1., Instruction Prefixes in Appendix B, Instruction Formats and
Encodings.
2.3.OPCODE
The primary opcode is either 1 or 2 bytes. An additional 3-bit opcode field is sometimes encoded
in the ModR/M byte. Smaller encoding fields can be defined within the primary opcode. These
fields define the direction of the operation, the size of displacements, the register encoding,
condition codes, or sign extension. The encoding of fields in the opcode varies, depending on
the class of operation.
2.4.MODR/M AND SIB BYTES
Most instructions that refer to an operand in memory have an addressing-form specifier byte
(called the ModR/M byte) following the primary opcode. The ModR/M byte contains three
fields of information:
The mod field combines with the r/m field to form 32 possible values: eight registers and
24 addressing modes.
The reg/opcode field specifies either a register number or three more bits of opcode infor-
mation. The purpose of the reg/opcode field is specified in the primary opcode.
The r/m field can specify a register as an operand or can be combined with the mod field to
encode an addressing mode.
