3-1
CHAPTER 3
INSTRUCTION SET REFERENCE
This chapter describes the complete Intel Architecture instruction set, including the integer,
floating-point, MMX technology, Streaming SIMD Extensions, and system instructions. The
instruction descriptions are arranged in alphabetical order. For each instruction, the forms are
given for each operand combination, including the opcode, operands required, and a description.
Also given for each instruction are a description of the instruction and its operands, an opera-
tional description, a description of the effect of the instructions on flags in the EFLAGS register,
and a summary of the exceptions that can be generated.
3.1.INTERPRETING THE INSTRUCTION REFERENCE PAGES
This section describes the information contained in the various sections of the instruction refer-
ence pages that make up the majority of this chapter. It also explains the notational conventions
and abbreviations used in these sections.
3.1.1.Instruction Format
The following is an example of the format used for each Intel Architecture instruction descrip-
tion in this chapter:
