3-2
INSTRUCTION SET REFERENCE
CMCComplement Carry Flag
3.1.1.1.OPCODE COLUMN
The Opcode column gives the complete object code produced for each form of the instruction.
When possible, the codes are given as hexadecimal bytes, in the same order in which they appear
in memory. Definitions of entries other than hexadecimal bytes are as follows:
/digitA digit between 0 and 7 indicates that the ModR/M byte of the instruction uses
only the r/m (register or memory) operand. The reg field contains the digit that provides an
extension to the instruction's opcode.
/rIndicates that the ModR/M byte of the instruction contains both a register operand and
an r/m operand.
cb, cw, cd, cpA 1-byte (cb), 2-byte (cw), 4-byte (cd), or 6-byte (cp) value following the
opcode that is used to specify a code offset and possibly a new value for the code segment
register.
ib, iw, idA 1-byte (ib), 2-byte (iw), or 4-byte (id) immediate operand to the instruction
that follows the opcode, ModR/M bytes or scale-indexing bytes. The opcode determines if
the operand is a signed value. All words and doublewords are given with the low-order
byte first.
+rb, +rw, +rdA register code, from 0 through 7, added to the hexadecimal byte given at
the left of the plus sign to form a single opcode byte. The register codes are given in Table
3-1.
+iA number used in floating-point instructions when one of the operands is ST(i) from
the FPU register stack. The number i (which can range from 0 to 7) is added to the
hexadecimal byte given at the left of the plus sign to form a single opcode byte.
Opcode
Instruction
Description
F5
CMC
Complement carry flag
