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INSTRUCTION SET REFERENCE
CPUIDCPU Identification (Continued)
The first member of the Pentium
®
Pro processor family will return the following information
about caches and TLBs when the CPUID instruction is executed with an input value of 2:
EAX
03 02 01 01H
EBX
0H
ECX
0H
EDX
06 04 0A 42H
These values are interpreted as follows:
The least-significant byte (byte 0) of register EAX is set to 01H, indicating that the CPUID
instruction needs to be executed only once with an input value of 2 to retrieve complete
information about the processors caches and TLBs.
The most-significant bit of all four registers (EAX, EBX, ECX, and EDX) is set to 0,
indicating that each register contains valid 1-byte descriptors.
Bytes 1, 2, and 3 of register EAX indicate that the processor contains the following:
01HA 32-entry instruction TLB (4-way set associative) for mapping 4-KByte
pages.
02HA 2-entry instruction TLB (fully associative) for mapping 4-MByte pages.
03HA 64-entry data TLB (4-way set associative) for mapping 4-KByte pages.
The descriptors in registers EBX and ECX are valid, but contain null descriptors.
Bytes 0, 1, 2, and 3 of register EDX indicate that the processor contains the following:
42HA 256-KByte unified cache (the L2 cache), 4-way set associative, with a
32-byte cache line size.
0AHAn 8-KByte data cache (the L1 data cache), 2-way set associative, with a
32-byte cache line size.
04HAn 8-entry data TLB (4-way set associative) for mapping 4M-byte pages.
06HAn 8-KByte instruction cache (the L1 instruction cache), 4-way set associative,
with a 32-byte cache line size.
Intel Architecture Compatibility
The CPUID instruction is not supported in early models of the Intel486 processor or in any
Intel Architecture processor earlier than the Intel486 processor. The ID flag in the EFLAGS
register can be used to determine if this instruction is supported. If a procedure is able to set or
clear this flag, the CPUID is supported by the processor running the procedure.
