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INSTRUCTION SET REFERENCE
MASKMOVQByte Mask Write (Continued)
Intel C/C++ Compiler Intrinsic Equivalent
Pre-4.0 Intel C/C++ Compiler intrinsic:
void_m_maskmovq(__m64d, __m64n, char * p)
Version 4.0 and later Intel C/C++ Compiler intrinsic:
void_mm_maskmove_si64(__m64d, __m64n, char * p)
Conditionally store byte elements of d to address p. The high bit of each byte in the selector n
determines whether the corresponding byte in d will be stored.
Numeric Exceptions
None.
Protected Mode Exceptions
#GP(0)
For an illegal memory operand effective address in the CS, DS, ES, FS, or
GS segments.
#SS(0)
For an illegal address in the SS segment.
#PF (fault-code)For a page fault.
#UD
If CR0.EM = 1.
#NM
If TS bit in CR0 is set.
#MF
If there is a pending FPU exception.
#AC
For unaligned memory reference. To enable #AC exceptions, three condi-
tions must be true(CR0.AM is set; EFLAGS.AC is set; current CPL is 3)
Real Address Mode Exceptions
Interrupt 13
If any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH.
#UD
If CR0.EM = 1.
#NM
If TS bit in CR0 is set.
#MF
If there is a pending FPU exception.
