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INSTRUCTION SET REFERENCE
MASKMOVQByte Mask Write (Continued)
Virtual 8086 Mode Exceptions
Same exceptions as in Real Address Mode.
#AC
For unaligned memory reference if the current privilege level is 3.
#PF (fault-code) For a page fault.
Comments
MASKMOVQ can be used to improve performance for algorithms which need to merge data on
a byte granularity. MASKMOVQ should not cause a read for ownership; doing so generates
unnecessary bandwidth since data is to be written directly using the byte-mask without allo-
cating old data prior to the store. Similar to the Streaming SIMD Extension non-temporal store
instructions, MASKMOVQ minimizes pollution of the cache hierarchy. MASKMOVQ implic-
itly uses weakly-ordered, write-combining stores (WC). Refer to Section 9.3.9., Cacheability
Control Instructions in Chapter 9, Programming with the Streaming SIMD Extensions of the
Intel Architecture Software Developers Manual, Volume 1, for further information about non-
temporal stores.
As a consequence of the resulting weakly-ordered memory consistency model, a fencing oper-
ation such as SFENCE should be used if multiple processors may use different memory types to
read/write the same memory location specified by edi.
This instruction behaves identically to MMX instructions, in the presence of x87-FP instruc-
tions: transition from x87-FP to MMX technology (TOS=0, FP valid bits set to all valid).
MASMOVQ ignores the value of CR4.OSFXSR. Since it does not affect the new Streaming
SIMD Extension state, they will not generate an invalid exception if CR4.OSFXSR = 0.
