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INSTRUCTION SET REFERENCE
MOVMove to/from Control Registers (Continued)
The following side effects are implementation specific for the Pentium
®
Pro processors. Soft-
ware should not depend on this functionality in future Intel Architecture processors:
When modifying any of the paging flags in the control registers (PE and PG in register
CR0 and PGE, PSE, and PAE in register CR4), all TLB entries are flushed, including
global entries.
If the PG flag is set to 1 and control register CR4 is written to set the PAE flag to 1 (to
enable the physical address extension mode), the pointers (PDPTRs) in the page-directory
pointers table will be loaded into the processor (into internal, non-architectural registers).
If the PAE flag is set to 1 and the PG flag set to 1, writing to control register CR3 will
cause the PDPTRs to be reloaded into the processor.
If the PAE flag is set to 1 and control register CR0 is written to set the PG flag, the
PDPTRs are reloaded into the processor.
Operation
DEST
<
SRC;
Flags Affected
The OF, SF, ZF, AF, PF, and CF flags are undefined.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If an attempt is made to write invalid bit combinations in CR0 (such as
setting the PG flag to 1 when the PE flag is set to 0, or setting the CD flag
to 0 when the NE flag is set to 1).
If an attempt is made to write a 1 to any reserved bit in CR4.
If an attempt is made to write reserved bits in the page-directory pointers
table (used in the extended physical addressing mode) when the PAE flag
in control register CR4 and the PG flag in control register CR0 are set to 1.
Real-Address Mode Exceptions
#GP
If an attempt is made to write a 1 to any reserved bit in CR4.
Virtual-8086 Mode Exceptions
#GP(0)
These instructions cannot be executed in virtual-8086 mode.
