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INSTRUCTION SET REFERENCE
MOVNTPS—Move Aligned Four Packed Single-FP Non Temporal
(Continued)
Real Address Mode Exceptions
Interrupt 13
If any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH.
#UD
If CR0.EM = 1.
#NM
If TS bit in CR0 is set.
#UD
If CR4.OSFXSR(bit 9) = 0.
#UD
If CPUID.XMM(EDX bit 25) = 0.
Virtual 8086 Mode Exceptions
Same exceptions as in Real Address Mode.
#PF(fault-code) For a page fault.
Comments
MOVTNPS should be used when dealing with 16-byte aligned single-precision FP numbers.
MOVNTPS minimizes pollution in the cache hierarchy. As a consequence of the resulting
weakly-ordered memory consistency model, a fencing operation should be used if multiple
processors may use different memory types to read/write the memory location. Refer to Section
9.3.9., Cacheability Control Instructions in Chapter 9, Programming with the Streaming SIMD
Extensions of the Intel Architecture Software DeveloperÂ’s Manual, Volume 1, for further infor-
mation about non-temporal stores.
The usage of Repeat Prefix (F3H) with MOVNTPS is reserved. Different processor implemen-
tations may handle this prefix differently. Usage of this prefix with MOVNTPS risks incompat-
ibility with future processors.
