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INSTRUCTION SET REFERENCE
MOVNTQMove 64 Bits Non Temporal (Continued)
Real Address Mode Exceptions
Interrupt 13
If any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH.
#UD
If CR0.EM = 1.
#NM
If TS bit in CR0 is set.
#MF
If there is a pending FPU exception.
Virtual 8086 Mode Exceptions
Same exceptions as in Real Address Mode.
#AC
For unaligned memory reference if the current privilege level is 3.
#PF (fault-code) For a page fault.
Comments
MOVNTQ minimizes pollution in the cache hierarchy. As a consequence of the resulting
weakly-ordered memory consistency model, a fencing operation should be used if multiple
processors may use different memory types to read/write the memory location. Refer to Section
9.3.9., Cacheability Control Instructions in Chapter 9, Programming with the Streaming SIMD
Extensions of the Intel Architecture Software Developers Manual, Volume 1, for further infor-
mation about non-temporal stores.
MOVNTQ ignores the value of CR4.OSFXSR. Since it does not affect the new Streaming SIMD
Extension state, MOVNTQ will not generate an invalid exception if CR4.OSFXSR = 0.
