A-3
OPCODE MAP
A.1.2.Codes for Operand Type
The following abbreviations are used for operand types:
aTwo one-word operands in memory or two double-word operands in memory, depend-
ing on operand-size attribute (used only by the BOUND instruction).
bByte, regardless of operand-size attribute.
cByte or word, depending on operand-size attribute.
dDoubleword, regardless of operand-size attribute.
dqDouble-quadword, regardless of operand-size attribute.
p32-bit or 48-bit pointer, depending on operand-size attribute.
piQuadword MMX technology register (e.g. mm0)
ps128-bit packed FP single-precision data.
qQuadword, regardless of operand-size attribute.
s6-byte pseudo-descriptor.
ssScalar element of a 128-bit packed FP single-precision data.
siDoubleword integer register (e.g., eax)
vWord or doubleword, depending on operand-size attribute.
wWord, regardless of operand-size attribute.
A.1.3.Register Codes
When an operand is a specific register encoded in the opcode, the register is identified by its
name (for example, AX, CL, or ESI). The name of the register indicates whether the register is
32, 16, or 8 bits wide. A register identifier of the form eXX is used when the width of the register
depends on the operand-size attribute. For example, eAX indicates that the AX register is used
when the operand-size attribute is 16, and the EAX register is used when the operand-size at-
tribute is 32.
A.2.OPCODE LOOK-UP EXAMPLES
This section provides several examples to demonstrate how the following opcode maps are used.
Refer to the introduction to Chapter 3, Instruction Set Reference, in the Intel Architecture Soft-
ware Developers Manual, Volume 2 for detailed information on the ModR/M byte, register val-
ues, and the various addressing forms.
