B-1
APPENDIX B
INSTRUCTION FORMATS AND ENCODINGS
This appendix shows the formats and encodings of the Intel Architecture instructions. The main
format and encoding tables are Tables B-10, B-14, B-20, and B-23.
B.1.MACHINE INSTRUCTION FORMAT
All Intel Architecture instructions are encoded using subsets of the general machine instruction
format shown in Figure B-1. Each instruction consists of an opcode, a register and/or address
mode specifier (if required) consisting of the ModR/M byte and sometimes the scale-index-base
(SIB) byte, a displacement (if required), and an immediate data field (if required).
The primary opcode for an instruction is encoded in one or two bytes of the instruction. Some
instructions also use an opcode extension field encoded in bits 5, 4, and 3 of the ModR/M byte.
Within the primary opcode, smaller encoding fields may be defined. These fields vary according
to the class of operation being performed. The fields define such information as register encod-
ing, conditional test performed, or sign extension of immediate byte.
Almost all instructions that refer to a register and/or memory operand have a register and/or ad-
dress mode byte following the opcode. This byte, the ModR/M byte, consists of the mod field,
the reg field, and the R/M field. Certain encodings of the ModR/M byte indicate that a second
address mode byte, the SIB byte, must be used.
If the selected addressing mode specifies a displacement, the displacement value is placed im-
mediately following the ModR/M byte or SIB byte. If a displacement is present, the possible siz-
es are 8, 16, or 32 bits.
If the instruction specifies an immediate operand, the immediate value follows any displacement
bytes. An immediate operand, if specified, is always the last field of the instruction.
Figure B-1. General Machine Instruction Format
ModR/M Byte
7 6 5 4 3 2 1 07 6 5 4 3 2 1 0
7-6 5-3 2-0
7-6 5-3 2-0
T T T T T T T TT T T T T T T TMod Reg* R/MScale Index Base
d32 | 16 | 8 | None
d32 | 16 | 8 | None
Opcode
1 or 2 Bytes
(T Represents an
Opcode Bit)
SIB ByteAddress Displacement
(4, 2, 1 Bytes or None)
Immediate Data
(4,2,1 Bytes or None)
Register and/or Address
Mode Specifier
* Reg Field is sometimes used as
an opcode extension field (TTT).
