15. Pulse Triggered Flip-flop, Cont.

• Pulse Triggered flip-flop a is clock cycle-oriented device and recognizes both 1 and 0 signals:

  • Clock signal 1 does B = A and logic circuit input = B.

  • Clock signal 0 does A = logic circuit output.

• During 1st phase, when clock=1, previously-computed state becomes current state and is sent to the logic circuit.

• During 2nd phase, when clock=0, next state, computed by logic circuit, is stored in latch A.