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TABLE OF FIGURES
Figure 1-1.Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
Figure 2-1.The Processing Units in the P6 Family Processor Microarchitecture
and Their Interface with the Memory Subsystem. . . . . . . . . . . . . . . . . . . . . . .2-7
Figure 2-2.Functional Block Diagram of the P6 Family Processor Microarchitecture . . .2-10
Figure 3-1.P6 Family Processor Basic Execution Environment. . . . . . . . . . . . . . . . . . . . .3-2
Figure 3-2.Three Memory Management Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
Figure 3-3.Application Programming Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6
Figure 3-4.Alternate General-Purpose Register Names . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
Figure 3-5.Use of Segment Registers for Flat Memory Model. . . . . . . . . . . . . . . . . . . . . .3-8
Figure 3-6.Use of Segment Registers in Segmented Memory Model . . . . . . . . . . . . . . . .3-9
Figure 3-7.EFLAGS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11
Figure 4-1.Stack Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
Figure 4-2.Stack on Near and Far Calls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6
Figure 4-3.Protection Rings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
Figure 4-4.Stack Switch on a Call to a Different Privilege Level . . . . . . . . . . . . . . . . . . .4-11
Figure 4-5.Stack Usage on Transfers to Interrupt and Exception Handling Routines . . .4-15
Figure 4-6.Nested Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-20
Figure 4-7.Stack Frame after Entering the MAIN Procedure. . . . . . . . . . . . . . . . . . . . . .4-21
Figure 4-8.Stack Frame after Entering Procedure A . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-22
Figure 4-9.Stack Frame after Entering Procedure B . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-23
Figure 4-10.Stack Frame after Entering Procedure C . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-24
Figure 5-1.Fundamental Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
Figure 5-2.SIMD Floating-Point Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
Figure 5-3.Bytes, Words, Doublewords and Quadwords in Memory. . . . . . . . . . . . . . . . .5-2
Figure 5-4.Numeric, Pointer, and Bit Field Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4
Figure 5-5.Memory Operand Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7
Figure 5-6.Offset (or Effective Address) Computation. . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9
Figure 6-1.Operation of the PUSH Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-23
Figure 6-2.Operation of the PUSHA Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-24
Figure 6-3.Operation of the POP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-24
Figure 6-4.Operation of the POPA Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-25
Figure 6-5.Sign Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-25
Figure 6-6.SHL/SAL Instruction Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-29
Figure 6-7.SHR Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-30
Figure 6-8.SAR Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-31
Figure 6-9.SHLD and SHRD Instruction Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-32
Figure 6-10.ROL, ROR, RCL, and RCR Instruction Operations . . . . . . . . . . . . . . . . . . . .6-33
Figure 6-11.Flags Affected by the PUSHF, POPF, PUSHFD, and POPFD instructions . .6-43
Figure 7-1.Binary Real Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3
Figure 7-2.Binary Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
Figure 7-3.Real Numbers and NaNs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6
Figure 7-4.Relationship Between the Integer Unit and the FPU . . . . . . . . . . . . . . . . . . . .7-9
Figure 7-5.FPU Execution Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-10
Figure 7-6.FPU Data Register Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-10
Figure 7-7.Example FPU Dot Product Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-12
Figure 7-8.FPU Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-13
Figure 7-9.Moving the FPU Condition Codes to the EFLAGS Register. . . . . . . . . . . . . .7-16
Figure 7-10.FPU Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-17
Figure 7-11.FPU Tag Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20
