TABLE OF FIGURES
xiv
Figure 7-12.Contents of FPU Opcode Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-22
Figure 7-13.Protected Mode FPU State Image in Memory, 32-BitFormat . . . . . . . . . . . .7-22
Figure 7-14.Real Mode FPU State Image in Memory, 32-BitFormat . . . . . . . . . . . . . . . .7-23
Figure 7-15.Protected Mode FPU State Image in Memory, 16-BitFormat . . . . . . . . . . . .7-23
Figure 7-16.Real Mode FPU State Image in Memory, 16-BitFormat . . . . . . . . . . . . . . . .7-24
Figure 7-17.Floating-Point Unit Data Type Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-25
Figure 8-1.MMX Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2
Figure 8-2.MMX Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3
Figure 8-3.Eight Packed Bytes in Memory (at address 1000H). . . . . . . . . . . . . . . . . . . . .8-4
Figure 9-1.SIMD Floating-Point Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3
Figure 9-2.Packed Single-FP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3
Figure 9-3.Four Packed FP Data in Memory (at address 1000H) . . . . . . . . . . . . . . . . . . .9-5
Figure 9-4.SIMD Floating-Point Control/Status Register Format. . . . . . . . . . . . . . . . . . . .9-7
Figure 9-5.Packed Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9
Figure 9-6.Scalar Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-10
Figure 9-7.Packed Shuffle Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-15
Figure 9-8.Unpack High Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-16
Figure 9-9.Unpack Low Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-16
Figure 10-1.Memory-Mapped I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3
Figure 10-2.I/O Permission Bit Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5
Figure 11-1.EAX Return Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-6
Figure 11-2.CPUID Feature Field Information Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-6
Figure 11-3.CR4 Register Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-7
Figure E-1.Recommended Circuit for MS-DOS* Compatibility FPU
Exception Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-6
Figure E-2.Behavior of Signals During FPU Exception Handling. . . . . . . . . . . . . . . . . . . E-7
Figure E-3.Timing of Receipt of External Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-8
Figure E-4.Arithmetic Example Using Infinity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-12
Figure E-5.General Program Flow for DNA Exception Handler. . . . . . . . . . . . . . . . . . . E-24
Figure E-6.Program Flow for a Numeric Exception Dispatch Routine . . . . . . . . . . . . . . E-24
Figure F-1.Control Flow for Handling Unmasked Floating-Point Exceptions. . . . . . . . . . .F-6
