xv
TABLE OF TABLES
Table 2-1.Processor Performance Over Time and Other Intel Architecture
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
Table 3-1.Effective Operand- and Address-Size Attributes . . . . . . . . . . . . . . . . . . . . . .3-15
Table 4-1.Exceptions and Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-14
Table 5-1.Default Segment Selection Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8
Table 6-1.Move Instruction Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-21
Table 6-2.Conditional Move Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-22
Table 6-3.Bit Test and Modify Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-34
Table 6-4.Conditional Jump Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-37
Table 6-5.Information Provided by the CPUID Instruction . . . . . . . . . . . . . . . . . . . . . . .6-45
Table 7-1.Real Number Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5
Table 7-2.Denormalization Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7
Table 7-3.FPU Condition Code Interpretation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-14
Table 7-4.Precision Control Field (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-17
Table 7-5.Rounding Control Field (RC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18
Table 7-6.Rounding of Positive Numbers with Masked Overflow. . . . . . . . . . . . . . . . . .7-19
Table 7-7.Rounding of Negative Numbers with Masked Overflow. . . . . . . . . . . . . . . . .7-19
Table 7-8.Length, Precision, and Range of FPU Data Types. . . . . . . . . . . . . . . . . . . . .7-26
Table 7-9.Real Number and NaN Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-27
Table 7-10.Binary Integer Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-28
Table 7-11.Packed Decimal Integer Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-29
Table 7-12.Unsupported Extended-Real Encodings. . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-31
Table 7-13.Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-32
Table 7-14.Floating-Point Conditional Move Instructions. . . . . . . . . . . . . . . . . . . . . . . . .7-33
Table 7-15.Setting of FPU Condition Code Flags for Real Number Comparisons. . . . . .7-37
Table 7-16.Setting of EFLAGS Status Flags for Real Number Comparisons. . . . . . . . . .7-37
Table 7-17.TEST Instruction Constants for Conditional Branching . . . . . . . . . . . . . . . . .7-38
Table 7-18.Rules for Generating QNaNs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-44
Table 7-19.Results of Operations with NaN Operands. . . . . . . . . . . . . . . . . . . . . . . . . . .7-45
Table 7-20.Arithmetic and Non-arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . .7-48
Table 7-21.Invalid Arithmetic Operations and the Masked Responses to Them . . . . . . .7-53
Table 7-22.Divide-By-Zero Conditions and the Masked Responses to Them . . . . . . . . .7-54
Table 7-23.Masked Responses to Numeric Overflow. . . . . . . . . . . . . . . . . . . . . . . . . . . .7-55
Table 8-1.Data Range Limits for Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6
Table 8-2.MMX Instruction Set Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8
Table 8-3.Effect of Prefixes on MMX Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . .8-11
Table 9-1.Precision and Range of SIMD Floating-point Datatype . . . . . . . . . . . . . . . . . .9-5
Table 9-2.Real Number and NaN Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6
Table 9-3.Rounding Control Field (RC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
Table 9-4.Streaming SIMD Extensions Behavior with Prefixes . . . . . . . . . . . . . . . . . . .9-20
Table 9-5.SIMD Integer Instructions Behavior with Prefixes. . . . . . . . . . . . . . . . . . . . . .9-20
Table 9-6.Cacheability Control Instruction Behavior with Prefixes. . . . . . . . . . . . . . . . .9-20
Table 9-7.Cache Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-24
Table 10-1.I/O Instruction Serialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-7
Table 11-1.EAX Input Value and CPUID Return Values . . . . . . . . . . . . . . . . . . . . . . . . .11-5
Table 11-2.New P6-Family Processor Feature Information Returned by
CPUID in EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-6
Table A-1.EFLAGS Cross-Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Table B-1.EFLAGS Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
