2-2
INTRODUCTION TO THE INTEL ARCHITECTURE
executing programs created for the 8086 and 8088 processors on the new 32-bit machine. The
32-bit addressing was supported with an external 32-bit address bus, giving a 4-GByte address
space, and also allowed each segment to be as large as 4 GBytes. The original instructions were
enhanced with new 32-bit operand and addressing forms, and completely new instructions were
provided, including those for bit manipulation. The Intel386 processor also introduced paging
into the IA, with the fixed 4-KByte page size providing a method for virtual memory manage-
ment that was significantly superior compared to using segments for the purpose (it was much
more efficient for operating systems, and completely transparent to the applications without
significant sacrifice of execution speed). Furthermore, the ability to define segments as large as
the 4 GBytes physical address space, together with paging, allowed the creation of protected
flat model
1
addressing systems in the architecture, including complete implementations of the
widely used mainframe operating system UNIX.
The IA has been and is committed to the task of maintaining backward compatibility at the
object code level to preserve our customers very large investment in software, but at the same
time, in each generation of the architecture, the latest most effective microprocessor architecture
and silicon fabrication technologies have been used to produce the fastest, most powerful
processors possible. Intel has worked over the generations to adapt and incorporate increasingly
sophisticated techniques from mainframe architecture into microprocessor architecture. Various
forms of parallel processing have been the most performance enhancing of these techniques, and
the Intel386 processor was the first IA processor to include a number of parallel stages: six.
These are the Bus Interface Unit (accesses memory and I/O for the other units), the Code
Prefetch Unit (receives object code from the Bus Unit and puts it into a 16-byte queue), the
Instruction Decode Unit (decodes object code from the Prefetch unit into microcode), the
Execution Unit (executes the microcode instructions), the Segment Unit (translates logical
addresses to linear addresses and does protection checks), and the Paging Unit (translates linear
addresses to physical addresses, does page based protection checks, and contains a cache with
information for up to 32 most recently accessed pages).
The Intel486 processor added more parallel execution capability by (basically) expanding the
Intel386 processors Instruction Decode and Execution Units into five pipelined stages, where
each stage (when needed) operates in parallel with the others on up to five instructions in
different stages of execution. Each stage can do its work on one instruction in one clock, and so
the Intel486 processor can execute as rapidly as one instruction per CPU clock. An 8-KByte
on-chip L1 cache was added to the Intel486 processor to greatly increase the percent of
instructions that could execute at the scalar rate of one per clock: memory access instructions
were now included if the operand was in the L1 cache. The Intel486 processor also for the
first time integrated the floating-point math Unit onto the same chip as the CPU (refer to Section
2.3., Brief History of the Intel Architecture Floating-Point Unit) and added new pins, bits, and
instructions to support more complex and powerful systems (L2 cache support and multipro-
cessor support).
Late in the Intel486 processor generation, Intel incorporated features designed to support
energy savings and other system management capabilities into the IA mainstream with the
Intel486 SL Enhanced processors. These features were developed in the Intel386 SL and
Intel486 SL processors, which were specialized for the rapidly growing battery-operated
1.Requires only one 32-bit address component to access anywhere in the address space.
