2-3
INTRODUCTION TO THE INTEL ARCHITECTURE
notebook PC market. The features include the new System Management Mode, triggered by its
own dedicated interrupt pin, which allows complex system management features (such as power
management of various subsystems within the PC), to be added to a system transparently to the
main operating system and all applications. The Stop Clock and Auto Halt Powerdown features
allow the CPU itself to execute at a reduced clock rate to save power, or to be shut down (with
state preserved) to save even more power.
The Intel Pentium
®
processor added a second execution pipeline to achieve superscalar perfor-
mance (two pipelines, known as u and v, together can execute two instructions per clock). The
on-chip L1 cache has also been doubled, with 8 KBytes devoted to code, and another 8 KBytes
devoted to data. The data cache uses the MESI protocol to support the more efficient write-back
mode, as well as the write-through mode that is used by the Intel486 processor. Branch predic-
tion with an on-chip branch table has been added to increase performance in looping constructs.
Extensions have been added to make the virtual-8086 mode more efficient, and to allow for 4-
MByte as well as 4-KByte pages. The main registers are still 32 bits, but internal data paths of
128 and 256 bits have been added to speed internal data transfers, and the burstable external data
bus has been increased to 64 bits. The Advanced Programmable Interrupt Controller (APIC) has
been added to support systems with multiple Pentium
®
processors, and new pins and a special
mode (dual processing) has been designed in to support glueless two processor systems.
The Intel Pentium
®
Pro processor introduced Dynamic Execution. It has a three-way super-
scalar architecture, which means that it can execute three instructions per CPU clock. It does this
by incorporating even more parallelism than the Pentium
®
processor. The Pentium
®
Pro
processor provides Dynamic Execution (micro-data flow analysis, out-of-order execution, supe-
rior branch prediction, and speculative execution) in a superscalar implementation. Three
instruction decode units work in parallel to decode object code into smaller operations called
micro-ops. These go into an instruction pool, and (when interdependencies dont prevent) can
be executed out of order by the five parallel execution units (two integer, two FPU and one
memory interface unit). The Retirement Unit retires completed micro-ops in their original
program order, taking account of any branches. The power of the Pentium
®
Pro processor is
further enhanced by its caches: it has the same two on-chip 8-KByte L1 caches as does the
Pentium
®
processor, and also has a 256-KByte L2 cache that is in the same package as, and
closely coupled to, the CPU, using a dedicated 64-bit (backside) full clock speed bus. The L1
cache is dual-ported, the L2 cache supports up to 4 concurrent accesses, and the 64-bit external
data bus is transaction-oriented, meaning that each access is handled as a separate request and
response, with numerous requests allowed while awaiting a response. These parallel features for
data access work with the parallel execution capabilities to provide a non-blocking architec-
ture in which the processor is more fully utilized and performance is enhanced. The Pentium
®
Pro processor also has an expanded 36-bit address bus, giving a maximum physical address
space of 64 GBytes.
The Pentium
®
II processor added MMX instructions to the Pentium
®
Pro processor architec-
ture, incorporating the new slot 1 and slot 2 packaging techniques. These new packaging tech-
niques moved the L2 cache off-chip or off-die. The slot 1 and slot 2 package uses a single-
edge connector instead of a socket. The Pentium
®
II processor expanded the L1 data cache and
L1 instruction cache to 16 KBytes each. The Pentium
®
II processor has L2 cache sizes of 256
KBytes, 512 KBytes and 1 MByte or 2 MByte (slot 2 only). The slot 1 processor uses a half
clock speed backside bus while the slot 2 processor uses a full clock speed backside bus. The
