2-5
INTRODUCTION TO THE INTEL ARCHITECTURE
The table below shows the dramatic increases in performance and transistor count of the IA
processors over their history, as predicted by Moores Law, and also summarizes the evolution
of other key features of the architecture.
NOTES:
1. Performance here is indicated by Dhrystone MIPs (Millions of Instructions per Second) because even
though MIPs are no longer considered a preferred measure of CPU performance, they are the only
benchmarks that span all six generations of the IA. The MIPs and frequency values given here corre-
spond to the maximum CPU frequency available at product introduction.
2. Main CPU register size and external data bus size are given in bits. Note also that there are 8 and 16-bit
data registers in all of the CPUs, there are eight 80-bit registers in the FPUs integrated into the Intel386
chip and beyond, and there are internal data paths that are 2 to 4 times wider than the external data bus
for each processor.
3. In addition to the large general-purpose caches listed in the table for the Intel486 processor (8 KBytes
of combined code and data) and the Intel Pentium
®
and Pentium
®
Pro processors (8 KBytes each for
separate code cache and data cache), there are smaller special purpose caches. The Intel 286 has 6
byte descriptor caches for each segment register. The Intel386 has 8 byte descriptor caches for each
segment register, and also a 32-entry, 4-way set associative Translation Lookaside Buffer (cache) to
store access information for recently used pages on the chip. The Intel486 has the same caches
described for the Intel386, as well as its 8K L1 general-purpose cache. The Intel Pentium
®
and Pen-
tium
®
Pro processors have their general-purpose caches, descriptor caches, and two Translation Looka-
side Buffers each (one for each 8K L1 cache). The Pentium
®
II and Pentium
®
III processors have the
same cache structure as the Pentium
®
Pro processor except that the size of each cache is 16K.
Table 2-1. Processor Performance Over Time and Other
Intel Architecture
Key
Features
Intel
Processor
Date of
Product
Intro-
duction
Perform
-ance
in MIPs
1
Max. CPU
Frequency
at Intro-
duction
No. of
Transis
-tors on
the Die
Main
CPU
Register
Size
2
Extern.
Data
Bus
Size
2
Max.
Extern.
Addr.
Space
Caches
in CPU
Pack-
age
3
8086
19780.88 MHz29 K16161 MBNone
Intel 28619822.712.5 MHz134 K161616 MBNote 3
Intel386
DX
19856.020 MHz275 K32324 GBNote 3
Intel486
DX
19892025 MHz1.2 M32324 GB8KB L1
Pentium
®
199310060 MHz3.1 M32644 GB16KB L1
Pentium
®
Pro
1995440200 MHz5.5 M326464 GB16KB L1;
256KB or
512KB L2
Pentium II
®
1997466
266
7 M326464 GB32KB L1;
256KB or
512KB L2
Pentium
®
III
1999
1000
500
8.2 M
32 GP
128
SIMD-FP
64
64 GB
32KB L1;
512KB L2
