2-6
INTRODUCTION TO THE INTEL ARCHITECTURE
2.3.BRIEF HISTORY OF THE INTEL ARCHITECTURE FLOATING-
POINT UNIT
The IA Floating-Point Units (FPUs) before the Intel486 lack the added efficiency of integra-
tion into the CPU, but have provided the option of greatly enhanced floating-point performance
since the beginning of the family. (Since the earlier FPUs were on separate chips, they were
often referred to as numeric processor extensions (NPXs) or math coprocessors (MCPs).) With
each succeeding generation, Intel has made significant increases in the power and flexibility of
the FPU, and yet has maintained complete upward compatibility. The Pentium
®
Pro Processor
offers compatibility with object code for 8087, Intel 287, Intel 387 DX, Intel 387 SX, and Intel
487 DX math coprocessors and the Intel486 DX and Pentium
®
processors.
The 8087 numeric processor extension (NPX) was designed for use in 8086-family systems. The
8086 was the first microprocessor family to partition the processing unit to permit high-perfor-
mance numeric capabilities. The 8087 NPX for this processor family implemented a complete
numeric processing environment in compliance with an early proposal for IEEE Standard 754
for Binary Floating-Point Arithmetic.
With the Intel 287 coprocessor NPX, high-speed numeric computations were extended to 80286
high-performance multitasking and multi-user systems. Multiple tasks using the numeric
processor extension were afforded the full protection of the 80286 memory management and
protection features.
The Intel 387 DX and SX math coprocessors are Intels third generation numeric processors.
They implement the final IEEE Standard 754, adding new trigonometric instructions, and using
a new design and CHMOS-III process to allow higher clock rates and require fewer clocks per
instruction. Together, the Intel 387 math coprocessor with additional instructions and the
improved standard brought even more convenience and reliability to numeric programming and
made this convenience and reliability available to applications that need the high-speed and
large memory capacity of the 32-bit environment of the Intel386microprocessor.
The Intel486 processor FPU is an on-chip equivalent of the Intel 387 DX math coprocessor
conforming to both IEEE Standard 754 and the more recent, generalized IEEE Standard 854.
Having the FPU on-chip results in a considerable performance improvement in numeric-inten-
sive computation.
The Pentium
®
processor FPU has been completely redesigned over the Intel486 processor
FPU while maintaining conformance to both the IEEE Standard 754 and 854. Faster algorithms
provide at least three times the performance over the Intel486 processor FPU for common
operations including ADD, MUL, and LOAD. Many applications can achieve five times the
performance of the Intel486 processor FPU or more with instruction scheduling and pipelined
execution.
2.4.INTRODUCTION TO THE P6 FAMILY PROCESSORS
ADVANCED MICROARCHITECTURE
The P6 Family processors (introduced by Intel in 1995) represent the earliest implementation of
most recent processor in the IA family. Like its predecessor, the Pentium
®
processor (introduced
