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INSTRUCTION SET REFERENCE
FXSAVEStore FP and MMX
State And Streaming SIMD
Extension State (Continued)
The FSAVE format for FTW can be recreated from the FTW valid bits and the stored 80-bit FP
data (assuming the stored data was not the contents of MMX technology registers) using the
following table:
The J-bit is defined to be the 1-bit binary integer to the left of the decimal place in the signifi-
cand. The M-bit is defined to be the most significant bit of the fractional portion of the signifi-
cand (i.e., the bit immediately to the right of the decimal place).
When the M- bit is the most significant bit of the fractional portion of the significand, it must be
0 if the fraction is all 0s.
If the FXSAVE instruction is immediately preceded by an FP instruction which does not use a
memory operand, then the FXSAVE instruction does not write/update the DP field, in the
FXSAVE image.
MXCSR holds the contents of the SIMD floating-point Control/Status Register. Refer to the
LDMXCSR instruction for a full description of this field.
The fields XMM0-XMM7 contain the content of registers XMM0-XMM7 in exactly the same
format as they exist in the registers.
Exponent
all 1s
Exponent
all 0s
Fraction
all 0s
J and M
bits
FTW valid
bit
x87 FTW
0
0
0
0x
1
Special10
0
0
0
1x
1
Valid00
0
0
1
00
1
Special10
0
0
1
10
1
Valid00
0
1
0
0x
1
Special10
0
1
0
1x
1
Special10
0
1
1
00
1
Zero01
0
1
1
10
1
Special10
1
0
0
1x
1
Special10
1
0
0
1x
1
Special10
1
0
1
00
1
Special10
1
0
1
10
1
Special10
For all legal combinations above
0
Empty11
