B-16
INSTRUCTION FORMATS AND ENCODINGS
SETcc Byte Set on Condition
register
0000 1111 : 1001 tttn : 11 000 reg
memory
0000 1111 : 1001 tttn : mod 000 r/m
SGDT Store Global Descriptor Table Register0000 1111 : 0000 0001 : mod 000 r/m
SHL Shift Left
register by 1
1101 000w : 11 100 reg
memory by 1
1101 000w : mod 100 r/m
register by CL
1101 001w : 11 100 reg
memory by CL
1101 001w : mod 100 r/m
register by immediate count
1100 000w : 11 100 reg : imm8 data
memory by immediate count
1100 000w : mod 100 r/m : imm8 data
SHLD Double Precision Shift Left
register by immediate count
0000 1111 : 1010 0100 : 11 reg2 reg1 : imm8
memory by immediate count
0000 1111 : 1010 0100 : mod reg r/m : imm8
register by CL
0000 1111 : 1010 0101 : 11 reg2 reg1
memory by CL
0000 1111 : 1010 0101 : mod reg r/m
SHR Shift Right
register by 1
1101 000w : 11 101 reg
memory by 1
1101 000w : mod 101 r/m
register by CL
1101 001w : 11 101 reg
memory by CL
1101 001w : mod 101 r/m
register by immediate count
1100 000w : 11 101 reg : imm8 data
memory by immediate count
1100 000w : mod 101 r/m : imm8 data
SHRD Double Precision Shift Right
register by immediate count
0000 1111 : 1010 1100 : 11 reg2 reg1 : imm8
memory by immediate count
0000 1111 : 1010 1100 : mod reg r/m : imm8
register by CL
0000 1111 : 1010 1101 : 11 reg2 reg1
memory by CL
0000 1111 : 1010 1101 : mod reg r/m
SIDT Store Interrupt Descriptor Table Register0000 1111 : 0000 0001 : mod 001 r/m
SLDT Store Local Descriptor Table Register
to register
0000 1111 : 0000 0000 : 11 000 reg
to memory
0000 1111 : 0000 0000 : mod 000 r/m
Table B-10. Integer Instruction Formats and Encodings (Contd.)
Instruction and Format
Encoding
